VHDL code for demultiplexer using dataflow (truth table) method – 1:4 Demux Usually, we see the truth table is used to code in the behavioral architecture. However, it is possible to use the truth table of a digital electronic circuit in the dataflow architecture too. This demux code is a perfect example of doing that. USEFUL LINKS to VHDL CODES. Refer following as well as links mentioned on left side panel for useful VHDL codes. D Flipflop T Flipflop Read Write RAM 4X1 MUX 4 bit binary counter Radix4 Butterfly 16QAM Modulation 2bit Parallel to serial. USEFUL LINKS to Verilog Codes. Following are the links to useful Verilog codes.
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When we implement a digital hardware architecture, we often need to select an input to our logic between several different inputs. This selection logic is called digital multiplexer or MUX.
We name it digital multiplexer, to distinguish it from an analog multiplexer. An analog multiplexer implements the same function as digital MUX selecting the source of a signal from different analog source instead of digital.
As clear in Figure1, a MUX can be visualized as an n-way virtual switch whose output can be connected to one of the different input sources. On the left side of the Figure1, you can see the typical MUX representation. The number near the input ports indicates the selector value used to route the selected input to the output port.
VHDL implementation of a digital MUX
The digital MUX is one of the basic building blocks of a digital design. Using the VHDL we have basically two different ways to describe a digital MUX:
- Concurrent description
- Sequential description
Both the descriptions are totally equivalent and implement the same hardware logic. You can use concurrent or sequential depending on your coding style.
Here below is represented a 4-way mux using a sequential representation
MUX description using SEQUENTIAL VHDL statement
Vhdl Code For 1 To 4 Demultiplexer Using Dataflow Modelling
Here below is represented a 4-way mux using a concurrent representation of SELECT statement
MUX description using SELECT VHDL statement
Another VHDL description of a 4-way mux using a concurrent representation is given below
MUX description using simple CONCURRENT VHDL statement
In Figure 2, Figure 3, Figure 4, are reported the implementation on Cyclone IV FPGA of the sequential and concurrent implementation of the VHDL code reported above. As clear, the circuit implementation is the same for both different VHDL coding style even if the RTL view can be different.
VHDL – MUX implementation using an array structure
If the number of the MUX input is a power of two, we can take advantage of the VHDL syntax, implementing the MUX in a very compact VHDL description.
To take advantage of the power of two number of input, we use the VHDL array structure.
In the VHDL code below, we define a user type that is an array of a signal using the same VHDL type of the MUX input.
The selector signal will be used as the index of the array.
The VHDL code is very compact and efficient as we can see below.
MUX description using simple ARRAY VHDL statement
Figure 6 reports the RTL and technology view of the MUX implementation using the array architecture implementation. As clear, the final implementation is totally equivalent to the concurrent or sequential one.
MUX VHDL Simulation
Figure 6 shows the MUX implementation. The MUX output the input value depending on the selector signal
Conclusion
In this post, we addressed different ways to implement digital MUX in VHDL:
- VHDL Concurrent MUX implementation
- VHDL Sequential MUX implementation
- VHDL array based MUX implementation, when the input signals are a power of two
All the different VHDL descriptions are mapped into the same hardware.
References
[1] https://en.wikipedia.org/wiki/Multiplexer
[2] www.altera.com
[3] www.xilinx.com
[4] RTL HARDWARE DESIGN USING VHDL Coding for Efficiency, Portability, and Scalability – PONG P.CHU
Vhdl Code For 1 To 4 Demultiplexer Using Case Statement
4X1 MUX VHDL source code
This page of VHDL source code covers 4X1 MUX vhdl code.
VHDL Code
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity depun_mux_out is
Port ( in1 : in std_logic; -- mux input1
in2 : in std_logic; -- mux input2
in3 : in std_logic; -- mux input3
in4 : in std_logic; -- mux input4
sel : in std_logic_vector(1 downto 0); -- selection line
dataout : out std_logic); -- output data
end depun_mux_out;
architecture Behavioral of depun_mux_out is
begin
-- This process for mux logic
process (sel, in1, in2, in3, in4)
begin
case SEL is
when '00' => dataout <= in1;
when '01' => dataout <= in2;
when '10' => dataout <= in3;
when '11' => dataout <= in4;
when others => dataout <= '0';
end case;
end process;
end Behavioral;
USEFUL LINKS to VHDL CODES
Refer following as well as links mentioned on left side panel for useful VHDL codes.
D Flipflop
T Flipflop
Read Write RAM
4X1 MUX
4 bit binary counter
Radix4 Butterfly
16QAM Modulation
2bit Parallel to serial